1. Field of the Invention
The present invention relates to semiconductor wafer processing and, more specifically, to embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation.
2. Description of the Related Art
Thermal anneals are often performed during middle of the line (MOL) semiconductor wafer processing in order to repair damage caused by the implantation of dopants (e.g., source/drain dopants), to diffuse dopants, to activate those dopants, to change the state of semiconductor material (e.g., to crystallize or recrystallize semiconductor material), etc. Thermal anneals can also be used to passivate an interface between different materials (e.g., an interface between a semiconductor layer and a dielectric layer) when performed in the presence of a gas, such as hydrogen. It would be advantageous to be able to perform a thermal anneal following back end of the line (BEOL) metal wiring layer formation; however, the temperature and processing time typically required for such thermal anneals can degrade the reliability of the metal wiring and, thereby impact performance.